The present invention relates to sample and hold amplifiers (SHAs) and, in particular, to reducing voltage offset errors that can be induced by pre-amplifiers that drive SHAs.
Sample and hold amplifiers, as their name implies, are electronic devices that sample a time-varying voltage and amplify it with predetermined gain (sometimes, unity gain). Switched capacitor amplifiers, switched capacitor integrators and switched capacitor filters are examples of circuit systems that use SHAs at their input. An input voltage is sampled by the SHA and held for a predetermined time so that it may be processed by subsequent circuit stages in the system. A pre-amplifier is often used at the input of a SHA.
SHAs, therefore, include a switch array that connects internal capacitors to an input voltage during a sampling operation. The switch array disconnects the capacitors from the input signal and connects the capacitors to other reference voltages during other phases of operation. The switch array is made up of a variety of transistor switches that are driven to be conductive and non-conductive as appropriate during the various phases of operation. Although transistors ideally should conduct no current when driven to be non-conductive, current leakage can occur at times, particularly when the SHA is operating at high temperature (in excess of 120° C.). The leakage problem manifests itself as a current drawn from the input source. If the input voltage source cannot supply the current that SHA demands, a pre-amplifier is often placed at the input of the SHA. Use of preamplifiers, however, induces errors of their own, discussed below in the context of an analog to digital converter.
Analog to digital converters (ADCs) are known circuits that sample an analog voltage within a predetermined voltage range and generate a digital code representing the voltage's magnitude. A variety of ADC architectures are available to circuit designers, including the successive approximation register (SAR) ADC 100, shown in FIG. 1 in block diagram form.
The SAR ADC 100 typically includes a sample & hold digital to analog converter (“SHA/DAC”) 110, a comparator 120, and a decode logic 130. The SHA/DAC 110 may sample the analog input signal (VIN) and generate test voltages (VTEST) during bit trials. The SHA/DAC 110 may include a capacitor array that includes a plurality of binary weighted capacitors (C to 2N-1C) The array may include a capacitor for each of the N bit positions of the output code. Each capacitor may be coupled at a bottom plate to a three-position switch that selectively connects the plate to the input voltage VIN, to a reference voltage (VREF) or to ground.
The comparator 120 may compare the SHA/DAC's test voltage to ground or some other reference voltage. The decode logic 130 may interpret the comparator's output and generate an N bit output code. In the ADC 100 illustrated in FIG. 1, the SHA is integrated with a SHA/DAC 110 to generate test voltages to the comparator. The SHA/DAC 110 includes the switched capacitor array in which the above-mentioned errors can arise.
The ADC may operate in two modes, a sampling mode and a bit-trial mode. During the sampling mode, bottom plates of all switchable SHA/DAC capacitors are connected to VIN, and top plates of all capacitors are connected to ground. Therefore, all switchable capacitors develop a voltage −VIN across them (measured from top plate to bottom plate).
During the bit-trial mode, the SHA/DAC 110 iteratively tests each bit position in order, starting with a most significant bit (MSB). The top plates of all capacitors are disconnected from ground and connected to the input of the comparator. Switches of any previously-tested bit position are set to their derived values. Bit positions deemed to be a “1” are connected to VREF, and bit positions deemed to be a “0” are connected to ground. A switch of a next bit position to be tested is connected to VREF.
The comparator 120 compares the resulting voltage VTEST to the voltage on its second input (ground). If the VTEST<ground, the next bit position is determined to be a “1”. Otherwise, the next bit position is determined to be “0”. This operation repeats until all bit positions have been tested.
For example, to test the MSB bit position, the switch corresponding to the 2N-1C capacitor is connected to VREF and the switches of all other bit positions are connected to ground. Due to charge sharing among the capacitors, a test voltage VTEST is developed corresponding to ½*VREF−VIN. If the comparator determines that VTEST<ground, the MSB will be determined to be a “1”. Otherwise, the MSB will be determined to be a “0”.
For the next iteration, the MSB switch will be set to VREF if a “1” or to ground if a “0” and the switch of the next bit position (the 2N-2C capacitor) will be set to VREF. In this iteration, the SHA/DAC will develop a VTEST voltage corresponding to ¾*VREF−VIN if the MSB was determined to be a “1” or ¼*VREF−VIN if the MSB was determined to be a “0”. The SHA/DAC 110 proceeds in this manner until all N bits have been tested.
FIG. 2 is a circuit diagram illustrating implementation of the switched capacitor array used in a SHA. The switch is implemented as three transistors 210-230, each coupled to the bottom plate of its associated capacitor C. Transistor 210 is coupled to the input voltage VIN. Transistor 220 is coupled to VREF. Transistor 230 is coupled to ground.
In an ideal case, when the ADC is operating in sampling mode, transistors 220 and 230 are non-conductive, which causes the capacitor Ci to charge to input voltage VIN. In practice, however, the transistors 220, 230 are not perfectly non-conductive and, therefore, the capacitor Ci charges to an incorrect level. This problem can be pronounced when the system runs at high temperatures (ex., 150° C.). Thus, when the SHA/DAC 110 runs through its bit trials, it does so with an erroneous sampled voltage.
FIG. 3 is a block diagram of an ADC 300 with a preamplifier. The ADC 300 may include a preamplifier 310, a SHA/DAC 320, a comparator 330, and a decoder 340. The preamplifier 310 may receive an input signal VIN and generates an amplified signal VAMP at a predetermined gain (which may be unity in appropriate circumstances). The SHA/DAC 320 may receive the amplified signal VAMP and digital control signals B[N−1:0] and generates test voltages VTEST for bit trials. The comparator 340 may include inputs for the test voltages VTEST from the SHA/DAC and for a reference voltage (typically, ground). The decoder 340 may interpret output from the comparator 330 and build a digital code therefrom during the bit trials.
At the end of operation, the ADC 300 may generate an N bit digital code comprised of bits B[N−1:0]. The preamplifier 310 may amplify the input signal VIN to a level sufficient to drive the SHA/DAC capacitors and overcome current loss through the VREF− and ground-coupled transistor switches. Preamplifiers typically generate signal artifacts of their own, including voltage offsets that may reach as high as ±3 mV in an ADC that has a least significant bit (LSB) step size of 300 μV. Moreover, the voltage offsets tend to manifest themselves randomly from device to device because they arise from manufacturing process variations. Voltage offsets also can arise from insufficient open loop gain of the amplifier.
To overcome this problem, Enz proposed a preamplifier with an auto-zeroing operation. Enz, et al., Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization, Proc. IEEE, vol. 84, no. 11, pp. 1584-1614 (November 1996). However, the Enz scheme tends to have issues with stability and settling. In high accuracy ADC applications, it is necessary to reduce contributions of voltage offsets even further than is possible in the FIG. 3 architecture.
Therefore, there is a need in the art for a preamplification scheme for a sample and hold unit that substantially reduces preamplifier voltage offsets without requiring large capacitances.